The present invention relates, in general, to design of digital circuits, and more particularly to optimization of delay times in a large digital integrated circuit.
Optimization of the delay times in large digital integrated circuits typically uses a calculation of a total delay time for each signal path. The calculation is then compared with a predetermined target delay time for that signal path. The signal path is then modified so as to more closely achieve the predetermined target delay time. A typical method used to calculate the total delay time lacks accuracy but can calculate the total delay time rapidly. When compared with a more accurate but slower circuit simulator such as SPICE, the relative error of the typical method may be 20% to 30% even for the best case simulation. But a circuit simulator like SPICE is far too slow to use for delay optimization. With the increased speed of submicron integrated circuits, errors are often as large as the total delay between gates. Under some conditions these errors result in damaging absurdities such as negative delay times. As a result, the optimization process either fails completely or is not effective. Either eventuality results in a design which can only operate at a lower speed than would otherwise be possible or may have hidden faults which cause incorrect operation.
There is need for a method for optimization of digital circuit delays in high speed digital circuits which more accurately models the circuit delays, yet does not require excessive computation. Ideally the delay values computed by such a method should agree with the delay values calculated by a circuit simulator to within 3% to 5%. The method should ensure that any calculation errors are reasonable and that such errors can never cause the circuit optimization to fail.